The verification includes RTL simulation, gate level simulation and static timing analysis.
驗(yàn)證工作包括RTL級仿真 、 門級仿真和靜態(tài)時序分析.
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The design includes system level design, RTL level design and logic synthesis.
設(shè)計工作包括系統(tǒng)級設(shè)計 、 RTL級設(shè)計、邏輯綜合.
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Module level micro architecture design and RTL implementation. Chip level integration.
模塊級微架構(gòu)設(shè)計以及RTL實(shí)現(xiàn), 片級整合.
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Creating an effective RTL behavioral model.
建立了一種有效的RTL行為模型.
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RTL 8019 AS source code with ATMEGA 8515 ( schema ) complete source code, has been tested.
RTL8019AS源代碼ATMEGA8515 ( 架構(gòu) ) 完整的源代碼, 已經(jīng)過測試.
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The driver of RTL 8019 AS LLC layer.
而RTL8019AS的驅(qū)動程序設(shè)計屬于邏輯鏈路子層實(shí)現(xiàn)的范疇.
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With the introduction of ethernet controller RTL 8910 AS , the initializing, data sending and data receiving programs were deployed.
介紹了以太網(wǎng)控制芯片RTL8019AS.討論了如何在該模塊中實(shí)現(xiàn)網(wǎng)卡初始化及網(wǎng)卡收發(fā)數(shù)據(jù)的網(wǎng)絡(luò)通訊過程.
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The hardware platform mainly include AT 89 C 55 with 20 k bytes Flash, RTL 8019 AS and RTL 8029 AS, CPLD EPM 7128 S etc.
硬件平臺主要是由內(nèi)帶20k字節(jié)Flash的AT89C55,32k字節(jié) 容量的RAM62256, 網(wǎng)絡(luò)接口芯片RTL8019AS和RTL8029AS,做PCI-ISA橋的CPLDEPM7128S等組成.
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